A fiber optic communications link typically includes a transmitter which transmits and directs light emitted from a laser diode through a fiber optic cable. At the receiving end of the fiber optic cable the light is detected by a photo detector and converted into an electrical current. The current is converted to voltage by a transimpedance amplifier and then amplified by a limiting amplifier. The amplified voltage signal is applied to a clock and data recovery (CDR) circuit which extracts a clock signal from the received data and acquires the frequency of the incoming data by comparing the frequency of the clock signal to the frequency of the incoming data. The clock and data recovery circuit also acquires and tracks the phase of the incoming data, which is known as phase acquisition.
The frequency acquisition is typically acquired with a frequency lock loop (FLL) circuit and the phase acquisition is acquired with a phase lock loop (PLL) circuit. The FLL circuit typically includes a frequency detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO) and a digital divider. The PLL circuit typically includes the same components as the FLL, but utilizes a phase detector instead of a frequency detector.
Frequency acquisition is achieved by the FLL when the frequency of the recovered clock signal is equal to the frequency of the incoming data (e.g., fCLK=fDATA). One distinct drawback of a typical CDR circuit is that the FLL may falsely lock the clock signal to a higher harmonic (integer multiple) of the incoming data signal. In this case, the frequency of the clock signal is greater than the frequency of the data signal by an integer multiple of at least two (e.g., fCLK=K×fDATA, where K=2, 3, 4 . . . ). Hence, conventional CDR circuits may falsely lock the clock signal to a higher harmonic of the data signal.